Ever thought of how a small microchip is able to perform all the tasks and that too superbly? Ever thought of How these chips understand what to do and how to do?.
Well the Answer to this is Verilog.
So what’s this Verilog all about..?
It’s a hardware description language (HDL) which is used in modeling electronic systems and is the most widely used in designing, verifying, and implementing of digital logic chips as well as verifying analog and mixed signal circuits.
You might be wondering what a Verilog looks like or in my case the question was “how scary does it looks?” , when I first heard of it.
So here’s an Example
module main;
initial
begin
$display(“Hey Whats up!”);
$finish;
end
endmodule
Needless to explain the code above, and now u have an Idea that its nothing to be scared of.
Verilog was written by Phil Moorby and Prabhu Goel during the 1983/1984 as a HDL at Automated Integrated Design Systems which was then purchased by Cadence Design Systems in 1990 and till date Cadence is the Proprietor of Verilog.
After its first version with the increasing popularity of VHDL sometime in 1995, Cadence decided to make it available for open standardization. Verilog was moved to the public domain under the Open Verilog International (OVI) now called as Accellera organization. Verilog was later submitted to IEEE and no prizes for guessing that it did become an IEEE Standard and was nicknamed as Verilog 95.
Following Verilog 95 there were more IEEE standards Called as Verilog 2001 and Verilog 2005.These were more or less the corrections and added functionality over the previous versions.
Following Verilog-2005 was the System Verilog which is the superset of the former. It has many new features and capabilities to which is more of a boon to design-verification and design-modeling.
So next time If anyone tries to confuse you with their Programming Chip Theories, make sure you have the Answer with you…and that’s Verilog.
